1. Field of the Invention
The present invention relates to a high resistivity silicon wafer used as a substrate for a high frequency integrated circuit device and the like, and a method for manufacturing the same.
This application claims priority on Japanese Patent Application No. 2009-049908 filed on Mar. 3, 2009, Japanese Patent Application No. 2009-146996 filed on Jun. 19, 2009, and Japanese Patent Application No. 2009-200420 filed on Aug. 31, 2009, the contents of which are incorporated herein by reference.
2. Description of the Related Art
With the widespread use or miniaturization of high-frequency devices and the increase in the number of signals for mobile communication, near-field wireless LAN and the like, there has been an increasing demand for high-frequency circuits. A high resistivity is required for high-frequency circuit substrates. For such applications, other than very expensive compound semiconductors such as GaAs, CMOSs (Complementary Metal Oxide Semiconductors) using substrates made of single crystals of silicon obtained by the normal Czochralski method (CZ method) have been adopted. Further, the Floating Zone method (FZ method) has difficulties in manufacturing large-diameter single crystals and has problems relating to stability of quality and cost, resulting in drawbacks of not allowing a sufficient response to demand.
The CMOSs using the CZ substrates have been considered inappropriate due to large power consumption and a high possibility of substrate noise generation. However, as an improvement of the miniaturization technique, designing and the like has been promoted, the use of silicon wafers with high resistivity has allowed the problems above to be overcome.
In accordance with the CZ method, single crystals of silicon are manufactured by melting a raw material using a quartz crucible and being pulled directly from the melt. The resistivity of high-purity silicon is found to be 2.3×105 Ωcm, and is controlled to the desired resistivity by adding a slight amount of dopant such as boron (B: p-type) or phosphorus (P: n-type) to the silicon. Single crystals of silicon obtained by the CZ method usually contain about 20 ppma (16×1018 atoms/cm3 [ASTM F-121, 1979]) of oxygen eluted from the quartz crucible.
Oxygen of a relatively high concentration contained in silicon causes defects in the silicon wafer resulting in faulty characteristics of devices; while oxygen performs desired functions in the device fabrication process, such as preventing of slip extension, increasing of wafer strength, preventing of deformation, and forming of minute defects in the wafer which serves as gettering sites for trapping incorporated heavy metal ions that cause faulty operations in the devices.
As is well known, the resistivity of silicon wafers can be increased by reducing the amount of dopant. However, in the use of single crystals of silicon obtained by the CZ method, inevitably incorporated oxygen may change the resistivity significantly. Oxygen atoms are usually electrically neutral in silicon, and therefore, oxygen atoms have no impact on the electrical resistance thereof directly.
When a heat treatment process is conducted at a low temperature of 300 to 500° C. for a long time of about one hour or more, compounds are formed that fail to be transformed into stable SiO2 precipitates, and these compounds emit electrons showing characteristics similar to those of the donors. Therefore, the compounds are referred to as oxygen donors or thermal donors.
FIG. 1 is a view schematically illustrating the relationship between the number of thermal donors generated and the resistivity of wafers. In the case of low resistivity wafers with a normal resistivity of about 10 Ωcm, the amount of dopant is large enough in comparison with the number of thermal donors generated, whereby even if thermal donors are generated, the thermal donors have a minor impact on the resistivity. However, in the case of high resistivity wafers, the amount of dopant is small, whereby the resistivity is affected significantly by thermal donors. Particularly, in the case of p-type wafers, the conductivity caused by positive holes as acceptors lowers due to electron supply from donors; and thereby, the resistivity increases significantly and approaches infinity. Further, if the number of donors is increased and oxygen donor concentration exceeds acceptor concentration, conversion to n-type semiconductors occurs due to p/n type conversion, resulting in a reduction in resistivity. A heating process in the temperature range where thermal donors can be easily generated is necessarily performed as a heat treatment for an interconnection formation in the last stage of the device fabrication process.
The number of thermal donors generated is reduced in silicon wafers of which the oxygen concentration is lowered. Hence, there are proposed methods for manufacturing single crystals with low oxygen to reduce the oxygen content, such as applying the magnetic field applied Czochralski method (MCZ method) wherein single crystals are pulled from molten silicon liquid while applying a magnetic field thereto to control the flow, and the method wherein a quartz crucible is used, the inner surface of which is coated with SiC.
However, with regard to these methods for reducing oxygen content, there are technical limitations in oxygen reduction, causing an increase in cost. Furthermore, there is a problem in that the oxygen reduction causes a reduction in wafer strength, whereby defective products due to deformation may be easily produced in the device fabrication process.
An invention relating to a high resistivity wafer using a single crystal of silicon obtained by the CZ method and eliminating the influence of thermal donors and a method for manufacturing the same is disclosed in the brochure of International Patent Publication No. WO 00/55397. The invention is characterized in that a single crystal with a resistivity of 100 Ωcm or more, an initial interstitial oxygen (solid-solubilized oxygen) concentration of 10 to 25 ppma (7.9×1017 to 19.8×1017 atoms/cm3 [ASTM F-121, 1979]), that is, normal oxygen content obtained by the CZ method is processed into wafers, and then an oxygen precipitate treatment is applied to the wafer to reduce the residual interstitial oxygen concentration to 8 ppma or less (6.4×1017 atoms/cm3 [ASTM F-121, 1979]).
However, it is described that the conditions of the heat treatment method for reducing the residual interstitial oxygen concentration to 8 ppma or less should not be restricted particularly because oxygen precipitates have only to be formed as a result and the residual interstitial oxygen concentration has only to be reduced to 8 ppma or less. In examples, there is only small extent of explanation demonstrating a two-step heat treatment including a heating at 800° C. for 4 hours in an oxygen or nitrogen atmosphere and a heating at 1000° C. for 16 hours in an oxygen atmosphere, and a three-step heat treatment including a heating at 650° C. for 2 hours in an oxygen atmosphere, a heating at 800° C. for 4 hours in the same atmosphere, and a heating at 1000° C. for 16 hours in an oxygen atmosphere. The ranges of the heat treatment conditions and the like are not clearly defined.
The DZ-IG (Denuded Zone-Intrinsic Gettering) treatment is generally employed as a method for controlling the state of being of oxygen in the wafer thickness direction on which devices are to be formed. This is a heat treatment adapted for preparing a region at or in the vicinity of the wafer surface where devices are to be formed, that is, an active region, as a Denuded Zone (DZ), and forming defects due to oxygen precipitates having a function of trapping heavy metal ions and the like, which are incorporated impurities, in the interior of the wafer.
Generally, a three-step heat treatment is to be performed, including (1) an oxygen out-diffusion heat treatment at the high temperature for forming a DZ in the surface region, (2) a low-temperature heat treatment for forming precipitate nuclei (heat treatment for forming oxygen precipitate nuclei), and (3) a middle or high-temperature heat treatment for forming defects due to oxygen precipitates serving as gettering sites in the interior of the wafer (heat treatment for growing oxygen precipitates).
Japanese Patent Application, Publication No. 2002-100631 discloses an invention relating to wafer processing conditions, in which the DZ-IG treatment is applied to a high resistivity wafer with a resistivity of 100 Ωcm or more. This invention is characterized, as with the invention described in the brochure of International Patent Publication No. WO 00/55397, in that obtaining a wafer where an interstitial oxygen concentration at any portion of the wafer is 8 ppm or less, a DZ layer is included at or in the vicinity of the surface and an oxygen precipitate layer is included in a bulk portion, and the width of the transition region between the DZ layer and the oxygen precipitate layer is 5 μm or less.
In a method for manufacturing a wafer according to the invention described in Japanese Patent Application, Publication No. 2002-100631, a wafer is used which is processed from a single crystal with an initial interstitial oxygen concentration of 10 to 25 ppma obtained by the CZ method, the wafer is subjected to a four-step heat treatment including (a) a first heat treatment at 950 to 1050° C. for 2 to 5 hours, (b) a second heat treatment at 450 to 550° C. for 4 to 5 hours, (c) a third heat treatment at 750 to 850° C. for 2 to 8 hours, and (d) a fourth heat treatment at 950 to 1100° C., so that the interstitial oxygen concentration is reduced to 8 ppm or less as described above.
In such a case, it would appear that the first heat treatment indicated by (a) is an oxygen out-diffusion treatment for forming the DZ layer and the fourth heat treatment indicated by (d) is an oxygen precipitate treatment for forming gettering sites. However, the heat treatments indicated by (b) and (c) are for performing treatments for forming precipitate nuclei sufficiently to reduce the interstitial oxygen concentration to 8 ppm or less without fault.
However, it is not necessarily easy to reduce the solid-solubilized oxygen concentration to 8 ppm or less across all portions in the wafer thickness direction by the heat treatments, and many steps of heat treatments are required, resulting in an increase in fabrication costs. In addition, reducing the solid-solubilized oxygen concentration results in a great reduction of wafer strength, whereby wafer deformation or slip dislocation may easily occur in a high-temperature heat treatment performed in the device fabrication process even if the number of oxygen donors may be reduced.
In Japanese Patent No. 3985768, the above problems are solved by doping carbon to increase the depth of a p/n type conversion region to about 8 μm from the wafer surface. However, in the carbon doping, if a carbon concentration is high, a Dislocation Free (DF) ratio is reduced due to the occurrence of polycrystallization, so that a single crystal may not be pulled. In this regard, a constant upper limit exists in the carbon concentration, and a wafer doped with carbon with a high concentration of the upper limit or more cannot be manufactured.
In addition, in a carbon-doped wafer, the depth range of an n-type region generated by the p/n type conversion is increased to only about 10 μm at a maximum from the wafer surface as disclosed in Japanese Patent No. 3985768 due to the upper limit of a carbon concentration range required for pulling a single crystal.
From the demand for an increase of range of application frequencies referred to as high frequency, corresponding to recent device design conditions, the demand for the reduction of power consumption, and the demand for the miniaturization as a design rule, there are demands for increasing the depth range of an n-type region generated by the p/n type conversion to 20 μm to 60 μm, expanding the range in which the p/n type conversion does not occur, and precisely performing position control at such a deep depth.
Further, in a voltage controlled oscillator and the like which is used for a transmission circuit and the like of a cell phone, as illustrated in FIG. 23, an eddy current VCO-E flows due to a magnetic field VCO-B generated when a current flows through a coil VCO-C of a digital area VCO-D. The eddy current VCO-E becomes a loss current VCO-d to an analog area VCO-A, resulting in reduction of efficiency η.
In light of such circumstances, it is an object of the present invention to provide a high resistivity p-type wafer using a single crystal obtained by a CZ method and having superior characteristics of preventing a CMOS formed on a surface active region from suffering from a faulty operation, n-well separation and the like. In addition, the present invention achieves the following purposes.
1. To enable the forming of a p/n type conversion region in a depth range exceeding 10 μm while maintaining a single crystal. Particularly, to enable the forming of the p/n type conversion region in a deeper depth range as compared with a conventional carbon-doped wafer; and thereby, reducing current loss.
2. To enable the controlling of a boundary depth in which p/n type conversion occurs.
3. In detail, to enable the controlling of the boundary depth at least in a range of 10 μm to 70 μm from the wafer surface.
4. To provide a wafer and a method for manufacturing the same, which can maintain a p type throughout the depth, that is, prevent the occurrence of p/n type conversion, in a high resistivity wafer.